In the area of semiconductor device fabrication, the MOS transistor is a basic building block, wherein the transistor can be controlled to operate either in a digital or analog manner. In the fabrication of MOS transistors, source and drain regions are doped oppositely to that of a body region in a semiconductor substrate. For example, as illustrated in prior art FIG. 1, source/drain regions 12 are formed in a semiconductor body 14 of a MOS transistor, wherein the source/drain regions 12 are an n-type material and the body region 14 is a p-type material (an NMOS transistor). A gate structure 16, for example, a polysilicon gate electrode 18 overlying a gate dielectric 20, overlies a channel region 22 of the semiconductor body. Sidewall spacers 24 reside on lateral edges of the gate structure 16 to facilitate the spacing of extension regions 26 associated with the source/drains 12. Based on the gate structure 16, a distance between the source/drain regions 12 is defined, which is often referred to as a channel length “L”, while a depth of the transistor, or extent in which the transistor extends transverse to the channel, is often referred to as a width “W” of the device. The width-to-length ratio (W/L) is a factor that substantially influences the drive current of the device, as well as other device performance characteristics.
As transistor devices constantly get scaled down to improve device density, both the width “W” and the channel length “L” dimensions are reduced, giving rise to various fabrication and device performance issues. One problem associated with a reduction in the transistor width “W” is experienced when shallow trench isolation (STI) is employed for device isolation, and that problem is sometimes referred to as the inverse narrow width effect (INWE). The mechanisms by which the INWE arises are not fully understood, however, various hypotheses exist. For example, it is postulated that the INWE is related to fields generated by transistors that are concentrated at sharp corners between the semiconductor body and the trench isolation structures. In addition, or alternatively, the INWE may be influenced by the diffusion of dopant atoms from the semiconductor body into the isolation structures, thereby reducing the dopant concentration of the channel dopant regions of the transistor near the STI structure.
Referring to prior art FIG. 2, a portion of a partially fabricated semiconductor device is illustrated, wherein a plurality of isolation structures 30, or STI trenches, are formed in the semiconductor body 14, thereby separating the body into isolation regions 32 and active areas 34, respectively. Subsequently, transistor devices such as MOS transistors are formed in the active areas 34, wherein a width dimension “W” of the MOS transistors extends between the isolation structures 30 as illustrated. As MOS transistor scaling continues, the distance “W” between the isolation structures decreases.
As illustrated in prior art FIG. 3, after source/drain regions 12 and gate structures 16 are formed in the active areas, portions 40 of the active regions near the STI trenches 30 will tend to suffer from the INWE. In such instances, when the gate (not shown) is biased, the field lines that for at the overlapping gate electrode 18 are focused by the edge geometry of the channel, and therefore at the edges of the channel, and an inversion layer is formed at lower voltages than at the center portion of the device in the middle of the active area. Consequently, less bias is needed for application to the gate to invert the channel across its full width, thereby lowering the threshold voltage of the device. With a decrease in threshold voltage, sub-threshold leakage may undesirably increase. At large transistor widths “W” the above effect does not greatly influence the device performance, however, as “W” continues to scale downward, the impact of INWE is greater. For example, as illustrated in prior art FIGS. 4 and 5, a plan view of two portions of a MOS transistor are provided, wherein the two devices have differing transistors widths. For example, in prior art FIG. 4, an active area 50 is defined between two laterally extending STI isolation regions 52. A conductive gate electrode 54 extends vertically across the active area between the two isolation regions 52, thereby defining a channel region 56 thereunder in the active area. Due to the INWE, a region 58 exists under the channel near the STI that contributes to a reduced device threshold voltage. For a device width W1, the net impact of the region 58 due to the INWE is relatively insignificant, however, as illustrated in prior art FIG. 5, for smaller transistor widths W2, the INWE will have a substantially greater impact on the resulting device performance.
Therefore there remains a need in the art for improved STI processes and techniques that reduce or alter the impact of the INWE in order to reduce or mitigate the device performance problems associated therewith.